This invention relates generally to lithographic formation of integrated circuit patterns and, more specifically, relates to techniques for generating lithographic masks and sources under requirements of a predetermined (e.g., maximal) yield in the final device using lithographic optimization (e.g., source optimization, mask optimization, or source-mask optimization) based on a yield model.
Integrated circuits are typically fabricated by using optical lithography to print images of the circuit device structures in photoresist films, followed by a pattern transfer step such as an etch step. However, the required ultrafine dimensions used in modern integrated circuits put a severe strain on the resolution capabilities of available patterning processes, and on the performance of the devices themselves. As a result, it can be very difficult to devise mask features and process conditions (such as the appropriate distribution of light intensities with which to illuminate the mask, such distributions being referred to as sources) that yield functional circuits. Moreover, even after such conditions have been devised, the process of fabricating the devices can be extremely sensitive to the small fluctuations in process conditions that inevitably arise during manufacturing, such as variations in lithographic dose and focus, or in the actual size of the written features of the exposing masks, or in the precise relative positions with which the different levels of the circuit are overlaid against each other as they are patterned.